1. Field of the Invention
The present invention relates generally to high performance digital computers. In particular, the present invention relates to a system and method for generating timing pulses to optimally trigger and sequence the operation of functional units of a pipelined high-performance digital computer.
2. Description of the Related Art
One continuing problem with digital computers has been the demand for increased processing performance. This need for increased processing power has led to the development of systems operating at faster and faster clock frequencies. A number of pipelined systems have also been developed to further increase the processing performance of digital computers. However, such existing system are not able to fully realize optimum performance because of the strict adherence to either an exclusively synchronous system or an exclusively asynchronous system.
Most computer systems in the prior art are synchronous. Synchronous systems have a penalty associated with their operation since there may be differing propagation delays in various portions of the system. These propagation delays may depend on the functions being performed as well as the functional units performing the operations. For example, different portions of the circuit may have different amounts of logic, different amounts of pipeline logic, and different lengths of data paths between components. In any event, synchronous systems must account for the propagation delay of each functional unit and then set the clock period such that even the slowest function unit (i.e., the unit with the greatest propagation delays) can complete its function within a single clock period. Thus, the minimum period for the clock cycle is limited by the speed of the slowest components in the system.
This problem is further complicated by the fact that there may be significantly different delays between operations that are performed within a single chip such as a microprocessor and operations external to the chip. For example, calculations utilizing the internal registers and functional units of the microprocessor may be performed at a very fast rate while transferring the results from the microprocessor to system memory may require a rate several times slower than the rate for internal operations of the microprocessor. Thus, there is a need for a system that permits the each portion of the system to operate at its optimum speed while providing a synchronous system utilized by all portions of the system.
Another approach to increasing the speed of computer systems has been to develop asynchronous systems that do not rely on any master clock or synchronizing signal. In such asynchronous systems, each of the independent circuit units performs its function at its optimum speed and outputs the results to other components through complex protocols and methods. However, it is very difficult to model, embody, and use such systems. The asynchronous operation of such system adds many levels of complexity to the processes of designing, operating, and using such systems.
Therefore, there is a need for a pulse generator that is programmable to produce a plurality of independent pulse streams based on a synchronous master clock signal.